TexEDA Design GmbH

EFFICIENT WORK WITH LAYTOOLS /LAYFRAME!

LAYTOOLS

for MS-Windows, LINUX and Sun-UNIX

Supported layout formats
GDS2, CIF, DXF, GERBER(RS-274X), OASIS,
DBX (TexEDA's internal data format)
Supported netlist formats
HSpice, PSpice, EDIF, Verilog (structural),
XNDL (TexEDA's internal netlist format)
Service Tools for libraries based on supported formats
Command input from
keyboard, hot-key, menu bar, tool bars, or command file

LAYFRAME is a program for the efficient management of the user's design data as well as for convenient work with all LAYTOOLS programs (Layed, LAYCIR,LAYVER,...) and simulation tools from other companies (SIMetrix, Smash, ADS, MSIM).
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Design Flow

Components in LAYTOOLS

Layout Editor
LAYED
Layout Viewer
LAYVIEW

Layout Verification
LAYVER
Database Manager
DBXMAN

Schematic Editor
LAYCIR/SPE
Plotter Interface
LAYPLOT

Place and Route
LAYPAR
LAYPLACE
LAYROUTE

Download LAYTOOLS Demo

Associated Software:

Circuit Simulation:
    SIMetrix of SIMetrix Technologies
    ADS of Agilent Technologies
    SMASH of Dolphin Integration
    MSIM of Legend Design Technology

Editor

LAYED
is an IC layout editor

Features:

Advanced edit features
Schematic/Netlist Driven Layout Editor (SDLE/NDLE)
Online DRC
edit - in - place
reference libraries
any given scales and angles
Hierarchical data structures
256 Layers, 256 GDSII datatypes
Groups (cells or structures)
parametric groups (pGroups, pCells)
Evaluation of LAYVER results
Schematic (LAYCIR/SPE) interface (SDLE and crossprobing)
SIMetrix schematic interface (SDLE and crossprobing)

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Viewer

LAYVIEW
is an IC Layout and LAYVER Database viewer

Features:

low-cost program version derived from LAYED
display of DBX, GDS2, OASIS, CIF, DXF, and Gerber layout data
display of LAYVER results
32- and 64-bit program versions available

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Verification System

LAYVER
is a layout verification package

Features:

Design Rule Check (DRC)
huge set of layer operations including logical, selectional and sizing operations
special DRC and edge operations
error identification
graphical evaluation with LAYED
Full flexibility of circuit extraction - no fixed technologies
flexible definition of devices to be extracted
user-defined expressions for parameter extraction
parameter calculation
parasitics extraction
user-defined parameter tolerances for comparison
layout versus schematic comparison
cross-probing
schematic versus schematic comparison
Output facilities
output of compressed vector files for LAYPLOT
output of LAYVER results in the supported layout and netlist formats
32- and 64-bit program versions available

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Plotter Interface

LAYPLOT
is a LAYVER-database plot program for Windows-based printers and plotters

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Database Manager

DBXMAN
is a DBX library manager

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Place and Route

LAYPAR

Tools for automatic Place and Route of standard cell block designs with up to 100 000 cell instances

Features:

consideration of net priorities and pad locations
separate definition and routing of clock trees
automatic generation of scan paths
Power routing and Dual Voltage
calculation and output of parasitics (node capacitances)

Separate tools for placement, routing and display of results controlled by the user interface program PARDLG

LAYPLACE
is a program for automatic placement of cells

Features:

generation of feed cell instances dependent on a given quota and deviation
mirroring of cells and cell rows
working with user-controlled effort in pre-, coarse and fine placement

LAYROUTE
is a standard cell routing program

Features:
- global routing based on a user-defined grid
- feedthrough handling and overcell routing
- 3-layer channel routing
- generation of cell block layout in all supported layout formats
- consideration of locked regions by the routing process

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Schematic Editor

SPE/ LAYCIR
is a schematic capture package for entering schematic graphical data. LAYCIR is a new version of SPE used in LAYFRAME

Features:

Hierarchical Structures
Reference Libraries (Directories) used for several schematics
Netlister (XNDL, pSpice, Smash, VHDL, EDIF, SIMetrix, or template-driven)
callback parameter calculation using LAYED pGroup procedures
Crossprobing with LAYED (LAYVER-Evaluation)
Schematic Driven Layout Editing (SDLE) together with LAYED
The input file can be an ECS-Synario-ASCII-file
Simulation interfaces for SIMetrix, ADS, MSIM, and SMASH

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Trademarks