LayPAR - place and route
The LayPAR product comprises two components, LayPLACE and LayROUTE which may be controlled and executed independently or may be run seamlessly in sequence. LayPAR incorporates clock tree insertion and automatic generation of scan paths as well as handling dual voltage power rail cells as well as power and ground rail connection. The application will also calculate nodal capacitances (parasitics), carries out a post routing lvs, and generates a layout which may be directly integrated as a block into a mixed signal design.

The application is targeted at medium-sized designs (≤500,000 gates) for mixedsignal applications, integrating advanced algorithms which allow it to handle large numbers of cells and macros in an efficient manner without manual intervention.

Features
  • fast placement algorithms (multiple coarse and fine trials)
  • multilayer routing (channel router with over-cell and feed-through routing)
  • no restriction on position of local origin of base cells
  • separate options to control placement, routing, power, scan path, and parasitic extraction
  • clock trees may be defined and routed
  • automatic generation of scan path
  • power and ground rail waffle format supported
  • dual power rail option
  • reduction of redundant vias with special routing mode (wireMode option)
  • calculation and net-listing of parasitics
  • stand-alone option using text definitions of cells and floor-plan
  • integrated with LayED for graphical definition of cells, floor-plan and viewing database
  • generated layout may be interrogated for net names (database properties)
  • integrated with LayVER for post-routing verification
  • HSpice and PSpice net-lists may be imported using TexEDA conversion tools
  • generates comprehensive report files, nodal information, final net-list, and parasitic table