Foundries often define specific restrictions for certain parameters as die size when inviting customers to use their Multi Project Wafer (MPW) route to silicon. The advantages of such an approach when prototyping advanced and innovative circuits is clear - the reticle assembly is thereby straightforward. However, the circuit density of reticles in such cases is often low because there is much unused silicon area. LayMPW offers the foundries, and companies which may wish to submit multiple die for a single process run, to optimize MPW silicon area. Through the use of advanced architectural algorithms, die size restrictions can now be a thing of the past. Any number of die of unrestricted dimension may be defined and placed with a separation of a defined amount (say 100um).

LayMPW program runs from a file which defines a set of parameters for each separate design that is to be included in the reticle. These parameters include a reference instance name, a customer reference, a technology reference, the circuit identifier, the number of die needed after sawing, the die dimensions, whether the die may be rotated, and pre-placement information where this is required. Some die may be tagged as not required to be sawn (test inserts for process parameter checks, for example). LayMPW generates a layout of the completed reticle that can be viewed in LayVIEW launched directly from the tool which establishes an appropriate default viewing environment (layer colors, etc.). LayMPW operates independently from other LayTOOLS modules and as a result is not launched from within LayFRAME. A multi-project wafer will generally comprise a number of reticles placed in an array on the wafer, often with array elements missing where they do not lie completely within the wafer area.