LayCIR is a flexible and powerful full-function schematic capture environment developed particularly to enable circuit design engineers to enter schematics accurately, clearly and quickly. In addition, it provides the ability to cross-probe between schematic and layout views. LayCIR includes many powerful features including the availability of an unlimited hierarchy that can be navigated from the design entry window with a single command. It offers a rich selection of digital and analog net-list formats and is closely linked to simulation environments. When coupled with LayED, LayCIR provides a schematic or net-list driven layout mode in which the layout implementation is monitored using the schematic or net-list.

Highlights

• Enables rapid entry of complex schematics
• Includes comprehensive editing features
• Provides easy navigation of design hierarchy
• Allows calculation and display of parameters
• Generates net-lists in various digital and analog formats
• Flexibly programmable simulator interface to address any simulator
• Build-in simulator interfaces for Keysight ADS and Symica
• Enables schematic-driven layout (LayED)
• Allows LVS and cross-probing with layout (LayED)

Feature Details

• Graphical data may be created and edited in an hierarchical set of schematic drawings
• Edit flexibility includes copying between windows and sub-window drag
• Data elements include symbols, attributes, texts, wires, buses, bus taps, and pins (for wires and buses)
• Unlimited bus widths
• Deep "undo" stack (currently set at 64)
• No limit on design size or complexity
• Unlimited number of sheets in multiple sheet drawings
• Unlimited depth of design hierarchy
• Navigation of the design hierarchy is unrestricted and traversed from the design entry window
• Symbols for both primitive and sub-circuits can be auto-generated or customized
• Symbols, whether customized or auto-generated, have no port count limit
• Symbols are characterized using user-defined attributes that may be calculated from other attributes
• Schematics and symbols may be organized in an unlimited number of reference directories
• Flexibility is provided for the naming format of nets and buses
• Standard net-list output formats are provided (device and gate level – including HSpice, PSpice, Verilog, VHDL, Spectre).
• Hierarchical integrity checks may be carried out (ERC)
• Cross-probing between LayCIR and LayED may use the same system or different systems ("socket" connection)
• Schematic-driven layout (SDLE) possible when used with LayED
• Parametric cells sharing between LayCir and LayED