TexEDA Design GmbH was acquired by Silicon Radar GmbH

LayVER - Layout Verification
LayVER is a sophisticated and comprehensive layout verification package that provides a complete set of tools to validate IC designs of any size and complexity. It includes a rich set of database layer operations, spacing, intersection, extension, and sizing checks, as well as circuit extraction, parameter measurement and net-list comparison all under the same umbrella. LayVER's flexibility accommodates very complex design constructs and can adapt to special technology demands. Unlike some traditional verification programs that use fixed device structures, LayVER offers user-definable devices - any unique design structure may be identified and extracted as a device. Associated utilities support industry-standard database formats and net-list formats such as HSpice, PSpice, or EDIF. With its flexibility and sophisticated algorithms, LayVER delivers unmatched verification performance. The traditional DRC and LVS functions may be complemented with electrical rules checks and parasitic parameter extraction (LPE), including track resistance, contact and via capacitance, and the various components of 3D parasitic capacitance (area, lateral and fringing terms).

Basic Features
  • Operates directly on LayED databases (DBX), GDS2, DXF2D, CIF, GERBER (RS-274X) databases
  • Technology independent
  • Operations apply to polygons, paths, buses, edges, or text
  • No practical restrictions on data shape or database size
  • Comprehensive select, combinational (logical), and sizing operations
  • Full set of traditional design rules-checking commands and options
  • Includes checking filters (both geometric and nodal)
  • Reads and writes various net-list formats (HSpice, PSpice, EDIF)
  • Net-list devices may be combined (serial or parallel)
  • Parameter expressions accepted in net-list
  • Flexible device parameter extraction using user-defined expressions
  • Parameter tolerances may be defined for LVS net-list comparison
  • Provides antenna checks
  • Provides filler generation
  • Provides coverage (density) checks (global or local coverage)
  • Comprehensive graphical evaluation of results in LayED
  • Checks for soft connections
  • Allows gate-swapping (option for digital circuits)
  • Detects and identifies shorts
  • Launched from LayED, from a command window, or as a batch file
  • Integrated into LayFRAME to provide a technology solution
  • Postscript output command to plot LayVER layers
Advanced Features
  • Net-list to net-list comparison option
  • Unrestricted user-defined device
  • structures
  • Handles complex constructs such as
  • asymmetrical contact and via rules.
  • Device parameter extraction using
  • user-defined expressions
  • Comprehensive parasitic parameter
  • extraction (LPE)
  • Extracts vertical, lateral, and fringe
  • capacitance parasitics
  • Also extracts contact, via and track
  • resistance.
  • Allows definition of variables and
  • variable values
  • Variables allow system configuration
  • for optimal performance
  • Conditional branching at run time
  • according to database contents or
  • defined variables
  • All data extracted can be interrogated
  • either within LayVER or from LayED
  • Case-sensitive user-defined names