LayVER is a sophisticated and comprehensive layout verification package that provides a complete set of tools to validate IC designs of any size and complexity. It includes a rich set of database layer operations, spacing, intersection, extension, and sizing checks, as well as circuit extraction, parameter measurement and net-list comparison all under the same umbrella. LayVER's flexibility accommodates very complex design constructs and can adapt to special technology demands. Unlike some traditional verification programs that use fixed device structures, LayVER offers user-definable devices - any unique design structure may be identified and extracted as a device. Associated utilities support industry-standard database formats and net-list formats such as HSpice, PSpice, or EDIF. With its flexibility and sophisticated algorithms, LayVER delivers unmatched verification performance. The traditional DRC and LVS functions may be complemented with electrical rules checks and parasitic parameter extraction (LPE), including track resistance, contact and via capacitance, and the various components of 3D parasitic capacitance (area, lateral and fringing terms).