LayFrame - Design Manager
LayFRAME is a design manager that allows the user to manage his data efficiently. as well as to work conveniently with the IC-Studio / RF-Studio applications. It allows the user to use a reference data set (technologyspecific data) often referred to as a process design kit (pdk). Further, it handles all the design data in an object-oriented approach, identifying the library sources of all data, listing the objects in each one, and offering a choice of actions based on the nature of the data (edit, view, delete, report, copy, etc.).

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LayCir - Schematic Editor
LayCIR is a flexible and powerful full-function schematic capture environment developed particularly to enable circuit design engineers to enter schematics accurately, clearly and quickly. In addition, it provides the ability to cross-probe between schematic and layout views. LayCIR includes many powerful features including the availability of an unlimited hierarchy that can be navigated from the design entry window with a single command. It offers a rich selection of digital and analog net-list formats and is closely linked to simulation environments. When coupled with LayED, LayCIR provides a schematic or net-list driven layout mode in which the layout implementation is monitored using the schematic or net-list.

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LayED - Graphical Editor
LayED is a powerful all-angles graphics editor especially developed for the layout of complex integrated circuits, including Analog, RF, Digital, and Mixed-Signal designs. Editing features include a rich command set, hierarchically structured databases, very fast redraw speed and screen refresh. Data can be imported or exported in standard exchange formats (GDS2, OASIS, CIF, GERBER, DXF). Parametric cells (PGroups), schematic crossprobing, and a schematic-driven layout option facilitate accurate and productive layout generation.

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LayVER - Layout Verification
LayVER is a sophisticated and comprehensive layout verification package that provides a complete set of tools to validate IC designs of any size and complexity. It includes a rich set of database layer operations, spacing, intersection, extension, and sizing checks, as well as circuit extraction, parameter measurement and net-list comparison all under the same umbrella. LayVER's flexibility accommodates very complex design constructs and can adapt to special technology demands. Unlike some traditional verification programs that use fixed device structures, LayVER offers user-definable devices - any unique design structure may be identified and extracted as a device. Associated utilities support industry-standard database formats and net-list formats such as HSpice, PSpice, or EDIF. With its flexibility and sophisticated algorithms, LayVER delivers unmatched verification performance. The traditional DRC and LVS functions may be complemented with electrical rules checks and parasitic parameter extraction (LPE), including track resistance, contact and via capacitance, and the various components of 3D parasitic capacitance (area, lateral and fringing terms).

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LayPAR - place and route
The IC-Studio / RF-Studio Place and Route package, LayPAR, may be used as a stand-alone tool or as an integrated component of the RF/IC Studio suite. The application is targeted at medium-sized designs (≤500,000 gates) for mixedsignal applications, integrating advanced algorithms which allow it to handle large numbers of cells and macros in an efficient manner without manual intervention.

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LayMPW - MPW Reticle Assembly
Foundries often define specific restrictions for certain parameters as die size when inviting customers to use their Multi Project Wafer (MPW) route to silicon. The advantages of such an approach when prototyping advanced and innovative circuits is clear - the reticle assembly is thereby straightforward. However, the circuit density of reticles in such cases is often low because there is much unused silicon area. LayMPW offers the foundries, and companies which may wish to submit multiple die for a single process run, to optimize MPW silicon area. Through the use of advanced architectural algorithms, die size restrictions can now be a thing of the past. Any number of die of unrestricted dimension may be defined and placed with a separation of a defined amount (say 100um).

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